pallet10 ns8Programmable in the system(min 10000 Programming/erasing cycle)-PlDParameter Specification Quotation DataSheet-ICQQG

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Brand:

Intel Xilinx

Installation type:

- Surface mount Through-Hole

packing:

bulk pallet pipe bulk,pallet pallet,pallet pipe pipe,pallet

series:

MAX® II MAX® 7000 MAX® V MAX® 3000A MAX® 7000A MAX® 7000S MAX® 7000B MAX® 9000 CoolRunner II XC9500XL CoolRunner XPLA3 XA9500XL XA XC9500 XC9500XV

Encapsulation/Housing:

100-LBGA 64-TFBGA 144-TFBGA 64-TQFP 144-LQFP 100-LQFP 100-TFBGA 32-VFQFN Exposed Pad 48-VFQFN Exposed Pad 64-TQFP Exposed Pad 100-TQFP 256-LBGA 324-BGA 44-LCC(feedthrough) 44-TQFP 68-LCC(feedthrough) 84-LCC(feedthrough) 208-BFQFP 256-TFBGA 100-BQFP 132-TFBGA,CSPBGA 144-TFBGA,CSPBGA 256-BGA 160-BQFP 208-BFQFP Exposed Pad 240-BFQFP Exposed Pad 256-BBGA 352-LBGA Bare pad,Metal 280-TFBGA,CSPBGA 324-LBGA 160-BPGA 68-TFBGA 192-BPGA 56-LFBGA,CSPBGA 324-BBGA 48-FBGA,CSPBGA

Programmable type:

Programmable in the system EE PLD - Programmable in the system(min 10000 Programming/erasing cycle) Programmable in the system(min 1K Programming/erasing cycle)

Maximum delay time:

7 ns 5.4 ns 6.2 ns 20 ns 4.7 ns 7.5 ns 9 ns 10 ns 4.5 ns 5 ns 15 ns 3.5 ns 6 ns 4 ns 5.5 ns 12 ns 8.7 ns 9.1 ns - 11.2 ns 8.1 ns 6.1 ns 6.7 ns 4.6 ns 5.7 ns 10.8 ns 9.2 ns 7.1 ns 3.8 ns 15.5 ns

Number of logic elements/blocks:

2210 570 1270 12 240 80 40 160 2 4 8 16 32 10 20 35 - 24 6

Number of macro cells:

1700 440 980 192 64 32 128 256 512 160 320 560 - 36 72 144 288 384 108 216

choosed:

10 ns

Programmable in the system(min 10000 Programming/erasing cycle)